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电路设计->基础电路图->数字电路图->[VHDL实例]地址译码(for m68008)

[VHDL实例]地址译码(for m68008)

作者:dolphin时间:2011-05-03

-- M68008 Address Decoder

-- Address decoder for the m68008

-- asbar must be '0' to enable any output

-- csbar(0) : X00000 to X01FFF

-- csbar(1) : X40000 to X43FFF

-- csbar(2) : X08000 to X0AFFF

-- csbar(3) : XE0000 to XE01FF

library ieee;

use ieee.std_logic_1164.all;

entity addrdec is

port(

asbar : in std_logic;

address : in std_logic_vector(19 downto 0);

csbar : out std_logic_vector(3 downto 0)

);

end entity addrdec;

architecture v1 of addrdec is

begin

csbar(0) = '0' when

((asbar = '0') and

((address = X00000) and (address = X01FFF)))

else '1';

csbar(1) = '0' when

((asbar = '0') and

((address = X40000) and (address = X43FFF)))

else '1';

csbar(2) = '0' when

((asbar = '0') and

((address = X08000) and (address = X0AFFF)))

else '1';

csbar(3) = '0' when

((asbar = '0') and

((address = XE0000) and (address = XE01FF)))

else '1';

end architecture v1;


关键词: 实例 地址 译码 m68008

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